FIG. 10 is a cross-sectional view of a conventional stack-type nonvolatile semiconductor memory device disclosed in a document (IEDM 1989, pp583-586).
As shown in FIG. 10, the conventional nonvolatile semiconductor memory device has a tunnel insulating film 201 formed of a silicon substrate 200, source and drain regions 202a and 202b formed in the silicon substrate 200, stack cell electrodes 211 including a floating gate electrode 203 formed as a layer over the tunnel insulating film 201, an oxide-nitride-oxide (ONO) capacitor film 204 and a control gate electrode 205, a topside protective oxide film 206a formed over the stack cell electrodes 211, and an oxide film sidewall 206b formed on side surfaces of the topside protective oxide film 206a and the stack cell electrodes 211. The control gate electrode 205 has a lower electrode layer 205a formed of polysilicon and an upper electrode layer 205b made of a silicide. The nonvolatile semiconductor device has a memory cell transistor thus constructed.
An interlayer insulating film 209 formed of a silicon oxide film and a bit line 210 extending on the interlayer insulating film 209 are provided on the substrate. One of the source and drain regions 202a and 202b, i.e., the drain region 202b in this semiconductor device, is connected to the bit line 210 by a drain contact. The drain contact in this example of the conventional device is constituted by a contact pad 207 formed of a tungsten silicide on the drain region 202b, and a tungsten plug 208 extending through the interlayer insulating film 209 and connecting to the contact pad 207. The contact pad 207 and the stack cell electrodes 211 are electrically insulated from each other by the topside oxide film 206a and the oxide film sidewall 206b. The upper surface oxide film 206a on the control gate electrode 205 is also used as an etching hard mask when the stack cell electrodes 211 are formed by etching. The oxide film sidewall 206b is formed in such a manner that an oxide film formed by deposition is etched back by anisotropic etching so that the oxide film is left on the stack cell electrode 211 and the topside oxide film 206a. 
Therefore the insulation withstand voltage between the stack cell electrodes 211 and the contact pad 207 is determined by the film thickness of the topside oxide film 206a and the film thickness of the oxide film sidewall 206b on the control gate electrode 205.
In the thus-constructed conventional semiconductor memory device, the contact pads 207 can be formed in a self-alignment manner in correspondence with the source and drain regions 202a and 202b. That is, there is no need to provide a margin for positioning between a mask for patterning the stack cell electrodes 211 and a mask for forming the contact holes in which the tungsten plugs 208 are embedded. Therefore the distance between the groups of stack cell electrodes 211 can be reduced. In other words, the margin for alignment of the contact holes in which the tungsten plugs 208 are embedded can be increased. For this reason in particular, this structure is suitable for semiconductor device processes of finer rule.
In the process of fabricating the stack-type nonvolatile semiconductor device, however, a plurality of cleaning steps are performed after formation of the topside oxide film 206a on the control gate electrode 205 and before deposition for forming the sidewall oxide film.
For example, resist separation and cleaning are performed after ion implantation for forming the source and drain regions, and cleaning is performed before deposition for forming the sidewall oxide film. The silicon oxide film or other materials exposed on the substrate are not substantially etched by one step for such cleaning. However, they are etched to some extent by a plurality of steps for such cleaning. That is, the exposed portion of the topside protective film 206a on the control gate electrode 204 is reduced by the plurality of cleaning steps.
FIGS. 9A, 9B, and 9C are cross-sectional views showing steps of forming the semiconductor device described in the above-mentioned document. FIGS. 9A, 9B, and 9C show only steps after etching on the exposed portion of the topside oxide film 206a. 
As shown in FIG. 9A, the topside oxide film 206a on the control gate electrode 205 is reduced from the shape before cleaning indicated by the broken line in the figure so that each of the thickness and the width thereof is smaller.
Thereafter, in the step shown in FIG. 9B, an oxide film for forming the sidewall is deposited on the substrate and is then etched back by anisotropic etching to form the oxide film sidewall 206b on the side surfaces of the stack cell electrodes 211 and the on-gate protective film 206a. The oxide film sidewall 206b thereby formed is thinner in its portion Redge located above the upper end edge of the control gate electrode 205.
In the step shown in FIG. 9C, a tungsten silicide film is deposited on the substrate and contact pads 207 are formed by patterning from the tungsten silicide film. Further, interlayer insulating film 209 is deposited on the substrate, contact holes are formed through interlayer insulating film 209 so that they can reach the contact pad 207, and tungsten plugs 208 are formed so as to fill the contact holes. At this time, since the portion of the oxide film sidewall 206a is thinner, there is a possibility of the insulation withstand voltage between the contact pad 207 and the control gate electrode 205 being reduced.
In particular, in the nonvolatile semiconductor memory device having stack cell electrodes, because the upper end edge of the control gate electrode 205 to which a high voltage is applied is acute, and has electric field concentrated thereon electric breakdown can occur easily at the corresponding portion Redge, so that the reliability of the semiconductor device is low.
To solve this problem, the method of increasing the film thickness of the oxide film sidewall 206b may be used. However, if the film thickness of the oxide film sidewall 206b is reduced, the area of contact between the source or drain region 202a or 202b and the contact pad 207 deposited between the adjacent pair of the groups of stack cell electrodes 211 is reduced, resulting in an increase in the contact resistance between the source and drain regions 202a and 202b. 
An object of the present invention is to provide a method of manufacturing a stack-type nonvolatile semiconductor memory device including a memory cell transistor having contacts formed between groups of stack cell electrodes in a self-alignment manner to be connected to source and drain regions, the method enabling the semiconductor device to have a higher insulation withstand voltage by using a means for limiting the reduction in thickness of a portion of the insulating film between the contact pad and the control gate electrode.
To achieve the above-described object, according to the present invention, there is provided a method of manufacturing a semiconductor device including a memory cell transistor having stack cell electrodes, the method including a step (a) of forming on a semiconductor substrate in turn from bottom to top, a gate insulating film, a first conductor film, an intermediate insulating film, and a second conductor film, a step (b) of implanting ions of an impurity in the second conductor film, a step (c) of depositing a protective insulating film on the second conductive film after the step (b), a step (d) of performing, after the step (c), a heat treatment for activating the impurity implanted in the second conductor film; a step (e) of performing, after the step (d), patterning in turn the protective insulating film, the second conductor film, the intermediate insulating film and the first conductor on one film and on another to form the stack cell electrodes consisting of a floating gate electrode, an interlayer capacitor film and a control gate electrode, and an on-gate protective film in turn from bottom to top, a step (f) of forming an impurity diffusion layer in the semiconductor substrate by implantation of ions of an impurity with the stack cell gate electrode used as a mask, a step (g) of depositing an insulating film for a sidewall on the substrate and then performing anisotropic etching on the insulating film to form the sidewall on side surfaces of the stack cell electrode and the topside protective film, and a step (h) of forming a conductor contact adjacent to the sidewall, the conductor contact reaching the impurity diffusion layer.
According to this method, the density of the protective insulating film after the step (d) is high. Therefore the etching resistance of the protective insulating film at the time of removal and cleaning of a resist film in the patterning process of the stack cell electrode in the step (e) and the cleaning of the substrate surface in the step (g) is improved. An undesirable change in the shape of the on-gate protective insulating film is thereby limited, so that the reduction in thickness of the sidewall formed in the step (g) at the upper end edge of the control gate electrode is limited, thereby suitably sufficiently maintaining the insulation withstand voltage between a conductor contact the control gate electrode.
The temperature at which the heat treatment is performed in step (d) is set to such a point that the protective insulating film is densified, thereby further improving the etching resistance of the on-gate protective film.
Preferably, the heat treatment in the step (d) is performed in an inert atmosphere.
Preferably, in the step (c), a silicon oxide film is deposited as the protective insulating film.
If the above-described semiconductor device further has a peripheral circuit region including a MISFET, the step (a) is such that the first conductor film and the intermediate insulating film are formed in turn from bottom to top in the peripheral circuit region, the portions of the first conductor film and the intermediate insulating film located in the peripheral circuit region are then removed, and the gate insulating film and the second conductor film are thereafter formed in the peripheral circuit region; the step (b) is such that ions of the impurity are also implanted in a portion of the second conductor film located in the peripheral circuit region; the step (c) is such that the protective insulating film is also deposited on the portion of the second conductor film located in the peripheral circuit region; the step (e) is such that the portions of the second conductor film and the protective insulating film located in the peripheral circuit region are left; and the step (h) is such that a film of the conductor material is also deposited on the protective insulating film remaining in the peripheral circuit region. In this case, the method further comprises, after the step (h), a step of removing the protective insulating film in the peripheral circuit region, and performing patterning on the second conductor film to form a gate electrode of the MISFET. Thus, the semiconductor device having the memory cell region and the peripheral circuit region can be formed while the process steps are simplified.
Preferably, in such a case, the impurity implanted by ion implantation in step (b) is an n-type impurity.